On June 25, 2026, IBM announced what it calls the world's first sub-1 nanometer chip technology, a research milestone built on a new three-dimensional transistor architecture named nanostack. According to IBM, the design packs nearly 100 billion transistors onto a fingernail-sized die — roughly twice the density of the 2 nm node it announced in 2021 — and targets a 0.7 nm (7 angstrom) process generation.
The nanostack architecture vertically stacks and staggers two transistors, each composed of three 5 nm-thick nanosheets separated by about 9 nm. IBM reports — as company projections, not independently verified results — that this approach yields up to 50 percent more performance or 70 percent greater energy efficiency versus its 2 nm node, along with a 40 percent scaling improvement in SRAM bit cells that IBM says was demonstrated at VLSI 2026. Electron microscope images released with the announcement show structures at 4.5 nm resolution with individual silicon atoms visible, which IBM says demonstrates atomic-scale fabrication control.
What's new
- Node designation: 0.7 nm / 7 angstrom (what IBM describes as an industry-first sub-1 nm label)
- Transistor density: Nearly 100 billion transistors per fingernail-sized chip (IBM-reported)
- Architecture: Nanostack — vertically stacked, staggered nanosheet transistors with dual-channel engineering
- Projected gains: Up to 50% performance increase or 70% energy efficiency improvement vs. 2 nm node (company-reported projections, not measured production results)
- SRAM scaling: 40% improvement via staggered-channel bit-cell design, per IBM's VLSI 2026 presentation
- Research validation: IBM reports ultra-thin dielectric bonding, functional CMOS inverter operation, and dual-channel capability demonstrated
- Production timeline: IBM projects earliest adoption in 5 years, with mainstream foundry adoption expected within a decade
Why it matters
SRAM scaling has nearly stalled between recent process nodes — improving only a few percent from 3 nm to 2 nm — creating a bottleneck for AI workloads that demand high-bandwidth, low-latency memory. If realized, a 40 percent SRAM density gain at the sub-1 nm node would directly alleviate that pressure, letting designers fit more cache on die without expanding chip area. Because IBM does not manufacture commercial chips, the timeline hinges on foundry partners such as Rapidus (Japan) and Samsung (South Korea), which have already licensed IBM's 2 nm nanosheet IP. TSMC independently developed its own nanosheet transistors for 2 nm, suggesting the nanostack pattern could diffuse across the industry even without direct IBM partnerships.
Confirmed
- IBM announced the nanostack architecture and sub-1 nm research milestone on June 25, 2026, via its newsroom and research blog.
- The architecture stacks and staggers two transistors built from 5 nm-thick nanosheets, per IBM's published technical descriptions.
- IBM presented related SRAM bit-cell work at VLSI 2026 and released electron microscope images at 4.5 nm resolution.
Unknown
- Whether the 50% performance, 70% efficiency, and 40% SRAM figures hold up outside IBM's own modeling and demonstrations — all are company-reported projections.
- Whether any foundry will commit to the nanostack architecture, and on what timeline; the 5-year adoption estimate is IBM's own.
- Whether "sub-1 nm" reflects any physical gate dimension or is purely a marketing-equivalent node label.
Our take
The nanostack announcement is a credible research advance, but the "sub-1 nm" branding describes equivalent density, not physical gate length — a distinction the industry has blurred for decades. The real signal is that 3D sequential integration with material flexibility per layer now works at CMOS inverter level, giving foundries a path past the nanosheet wall. Commercial impact will arrive only when High NA EUV tooling (coming to IBM's Albany facility) and yield learning converge, likely late this decade.
