On August 26, 2026, NVIDIA announced NVLink Fusion with NVHBM, a co-designed platform that lets hyperscalers and AI-native companies deploy custom XPUs and CPUs into the NVIDIA AI infrastructure stack. The combination delivers up to 30% higher memory bandwidth, 25% more compute die area, and 15% lower HBM power usage compared with standard HBM4e, resulting in a 30% overall end-to-end XPU performance increase.

NVHBM achieves its gains by integrating a custom base die and PHY, moving the memory controller into the 3D HBM stack, and reducing I/O area requirements. This frees up to 67% of PHY and support area versus the JEDEC HBM4e standard and provides up to 80% more usable silicon across the layout. NVLink Fusion, now in its sixth generation, connects those custom XPUs, CPUs, and NVIDIA GPUs at rack scale through a chiplet architecture that bridges into the NVLink fabric, enabling single scale-up domains, efficient expert parallelism, and simplified data center operations.

What's new

  • NVHBM memory technology: Up to 30% more memory bandwidth per stack, 15% lower HBM power, and up to 25% additional compute die area versus standard HBM4e.
  • Area savings mechanism: Custom base die with integrated PHY moves the memory controller into the 3D HBM stack, shrinking interface connections and simplifying interposer routing.
  • NVLink Fusion chiplet: Sixth-generation NVLink fabric delivers up to 1.8 TB/s bidirectional bandwidth per chiplet, connecting custom XPUs and CPUs to NVIDIA GPUs, NVLink Switches, and MGX rack-scale systems.
  • First NVHBM collaborator: Amazon's Annapurna Labs will adopt NVHBM for its next-generation Trainium chips starting with Trainium4, enabling Amazon chips and NVIDIA GPUs to share a common rack-scale architecture.
  • Ecosystem partners: Marvell and Astera Labs are building custom connectivity solutions around NVLink Fusion; Marvell announced its collaboration in May 2025, and Astera Labs confirmed design wins in December 2025.

Why it matters

The announcement signals a shift from one-size-fits-all GPU clusters toward heterogeneous AI factories where custom XPUs, CPUs, and NVIDIA GPUs coexist in the same rack-scale domain. By standardizing the scale-up interconnect and memory interface, NVIDIA reduces the integration risk and qualification burden that has slowed custom silicon programs. For hyperscalers, this means faster time-to-market for workload-specific accelerators — inference serving, recommendation systems, multimodal pipelines — while preserving the software stack, networking, and rack architecture they already deploy. The 30% end-to-end XPU performance claim compounds bandwidth, area, and power gains at the chip level with rack-scale connectivity that supports advanced routing such as expert parallelism across thousands of accelerators.

Our take

NVIDIA is effectively turning its interconnect and memory IP into a platform service for custom silicon. The 30% end-to-end uplift is a modeled figure that assumes co-optimization of NVHBM and NVLink Fusion; real-world results will depend on each partner's XPU architecture, workload mix, and how tightly they integrate with the NVIDIA software stack. The Annapurna Labs commitment for Trainium4 is the strongest validation yet that major cloud providers see value in this semi-custom path, but volume deployment timelines remain undisclosed.

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