On August 26, 2026, NVIDIA published Day-0 inference results for Alibaba's Qwen3.8-Flash-Next. The model is a 176-billion-parameter multimodal mixture-of-experts design that previews the upcoming Qwen4 architecture. It activates 6 billion parameters per token and includes a 51-billion-parameter N-gram embedding table. The native context window is 262,144 tokens, extensible to 1 million tokens using YaRN scaling.
NVIDIA validated the model on its GB300 NVL72 rack-scale system. The platform integrates 72 Blackwell Ultra GPUs connected by a fifth-generation NVLink domain delivering 130 TB/s of all-to-all bandwidth. The company reports over 16,000 tokens per second per GPU and more than 200 tokens per second per user.
What's New
- Model: Qwen3.8-Flash-Next (176B total, 6B active, 51B N-gram embeddings)
- Architecture: Hybrid Gated DeltaNet (GDN) and Qwen Sparse Attention (QSA) — three GDN layers compress history into a fixed recurrent state; one QSA layer aggregates tokens into micro-blocks for block-level importance retrieval
- Context: 262,144 tokens native, extensible to 1M with YaRN
- Hardware: NVIDIA GB300 NVL72 (72 Blackwell Ultra GPUs, 130 TB/s NVLink)
- Performance: >16K tokens/sec/GPU, >200 tokens/sec/user; up to 7.6× prefill and 4.9× decode speedup vs. full attention; 8.6× prefill throughput vs. Qwen3.7-Plus at 1M-token context with 90% prefix-cache hit rate
- Local deployment: Also runs on DGX Station, DGX Spark clusters, and workstations with four RTX PRO 6000 Blackwell GPUs
- Software stack: SGLang, vLLM, TensorRT-LLM, NeMo AutoModel (SFT/LoRA), NeMo RL for reinforcement learning
- Availability: Weights on Hugging Face and ModelScope; try via QwenCloud
Why It Matters
The hybrid GDN/QSA design targets the memory and compute bottlenecks that appear when agentic coding workloads accumulate long contexts — system instructions, tool outputs, retrieved code, and multi-step reasoning traces. By compressing history in GDN layers and retrieving selectively in QSA layers, the model keeps both KV cache growth and attention compute bounded as context scales to 1 million tokens. The 51B N-gram embedding table acts as a trainable lookup for frequent local token patterns, reducing the main model's burden for common n-grams.
NVIDIA's rack-scale NVLink domain matters because MoE expert traffic must move across all 72 GPUs without crossing slower external networks. The 130 TB/s fabric eliminates that bottleneck, enabling the reported per-GPU throughput. The same model weights run from local workstations to the full rack, giving developers a consistent path from prototype to production serving.
Our Take
Qwen3.8-Flash-Next is a preview artifact — Alibaba is shipping the Qwen4 architecture early so developers can adapt tooling before the full family lands. The 176B/6B parameter ratio and 51B embedding table are unusual; quantization support (especially NVFP4) and offloading behavior for the embedding tables will determine real-world deployability on DGX Spark and workstation GPUs. NVIDIA's Day-0 numbers are FP8 on GB300 NVL72; further optimization is expected.
