NVIDIA has published benchmark results for its Vera CPU architecture inside the BlueField-4 STX Storage Processor, showing significant throughput gains over an unnamed x86 CPU across the storage primitives that underpin agentic AI workloads. The Vera CPU integrates 88 Olympus Armv9.2 cores with Spatial Multithreading, a Scalable Coherency Fabric delivering up to 3.4 TB/s of bisection bandwidth, and SOCAMM2 LPDDR5X memory providing up to 1.2 TB/s aggregate bandwidth.
The microbenchmarks isolate individual storage functions — encryption, decryption, Reed-Solomon recovery, CRC32C integrity checking, compression, decompression, and a multi-stage pipeline — using common libraries such as OpenSSL, Zstandard, and LZ4. Tests run in-memory within a single process, excluding file I/O, disk, and network bottlenecks to measure the processor's direct contribution.
What's new
- AES-128 encryption: up to 1.43x higher throughput
- AES-128 decryption: up to 1.29x higher throughput
- Reed-Solomon recovery: up to 3.26x higher throughput
- CRC32C integrity checking: up to 3.67x higher throughput
- Compression (Zstandard/LZ4): up to 3.29x higher throughput
- Decompression: up to 1.72x higher throughput
- Multi-stage storage pipeline: up to 3.21x higher throughput
NVIDIA positions these gains as enabling storage platforms to secure, protect, validate, and compress more data while reducing CPU, power, and cooling overhead. Higher compression throughput also helps lower storage capacity and bandwidth demands. The company notes that end-to-end system testing is still required to quantify complete storage-system or GPU-performance outcomes.
Why it matters
Agentic AI workflows generate thousands of concurrent storage operations per second as agents retrieve knowledge, access persistent memory, reuse KV cache data, and execute tools. Each operation may trigger encryption, checksumming, redundancy calculation, and compression on writes, with corresponding validation, decryption, decompression, and reconstruction on reads. When the CPU-side processing cannot keep pace with SSDs and networks, it becomes the limiting stage in the data path. Vera's architecture targets both per-core latency for sequential data-path operations and aggregate bandwidth for concurrent streams, aiming to keep storage services from constraining token generation.
Our take
The benchmarks demonstrate real silicon-level advantages for Arm-based storage processing, but the comparison x86 CPU is not identified by model or generation. Without that context, the multipliers are useful for understanding Vera's architectural balance — strong vector and cryptographic resources fed by high-bandwidth coherent fabric — but not for procurement decisions. The in-memory test methodology also means real-world gains will depend heavily on storage software stack efficiency and I/O subsystem design.
