6 results for “energy efficiency”
NVIDIA’s DSX bet is tokens per megawatt: Lambda reports 24% more HGX B200 throughput at 85% power. Eos + Emerald cut 4 MW to 3 MW for the grid — Flex-pattern proof, not a shipped DSX Flex site.
NVIDIA launched DSX MaxLPS, a full-stack platform that dynamically reallocates stranded power across GPU racks to fit up to 40% more compute in the same facility envelope. The system combines real-time power steering, workload-aware profiles, and 45°C liquid cooling to boost performance per watt by 1.3–1.5x on Blackwell and Vera Rubin systems.
IBM announced a research sub-1 nm (0.7 nm / 7Å) chip node using nanostack transistor stacking. It reports nearly 100 billion transistors per fingernail-sized die and projects higher performance or efficiency vs its 2 nm node — production is years out.
SenseTime has launched the Galaxy Project, a coordinated effort with nearly 20 partners to scale domestic AI chip infrastructure across China. The Galaxy Project represents a systematic attempt to solve the multi-chip fragmentation that.
NVIDIA unveiled NVLink Fusion, letting hyperscalers plug custom XPUs into its 72‑XPU NVLink domain and MGX rack architecture. The program cuts non‑differentiated engineering so silicon teams can ship custom accelerators faster while reusing proven power, cooling, and cluster software.
Researchers from Tsinghua University, Graz University of Technology, and the National Research Council of Italy have introduced a new artificial intelligence framework that. Energy consumption has become a primary constraint on AI scaling.